1. Field of the Invention
The present invention relates to a method of fabricating a flash memory, and more particularly, to a method of fabricating a stringerless flash memory to prevent stringer leakage and improve data retention ability.
2. Description of the Prior Art
A flash memory is a non-volatile memory, which can preserve data within the memory even when an external power supply is lost. Recently, because flash memory is re-writable and re-erasable, it has been widely applied in the fabrication of electrical products, such as mobile phones, digital cameras, video players, personal digital assistants (PDA) or system on a chip (SOC).
Please refer to FIG. 1 of a cross-sectional diagram of a prior flash memory cell 30. As shown in FIG. 1, the flash memory cell 30 comprises a substrate 10, a floating gate 14, an ONO dielectric layer 18 and a word line 20. The floating gate 14, normally made from polysilicon, is positioned between an insulating layer 12a and 12b. Doping regions 11a and 11b, functioning as a bit line, are formed beneath the insulating layer 12a and 12b, respectively. The doping region 11a and 11b may also function as a buried drain or a buried source. In addition, a tunneling oxide layer 13 is positioned between the floating gate 14 and the substrate 10. Hot electrons tunnel through the tunneling oxide layer 13 to get in or get out of the floating gate 14, thus achieving data accessing.
During the fabricating process of the flash memory cell 30, however, a polysilicon residue 22 occurs causing current leakage problems. The side wall of both the insulating layers 12a, 12b is hard to keep perpendicular to the substrate 10 since the angle between the two planes is changing with an adjusting of the process parameters, thereby forming the polysilicon residue 22. Please refer to FIG. 1, while the insulating layer 12a and 12b intersect the substrate 10 at an angle xcex8 greater than 90 degrees, the polysilicon residue 22 will form on the side wall of the insulating layer 12a and 12b as a result of an etching process to define patterns of both the word line 20 and the floating gate 14. The polysilicon residue 22 may also be called stringer. The polysilicon residue 22 on the side wall of the insulating layer 12a and 12b not only induces leakage currents but also affects the electrical performance of the flash memory cell, thus reducing data retention ability.
In order to prevent the occurrence of the stringer, precise control of the process parameters is required so as to form the angle xcex8 as close to a right angle as possible. Specifically, the side wall of the floating gate 14 must be vertical so as to keep the side wall of the insulating layers 12a and 12b perpendicular to the surface of the substrate 10. In this case, however, the process window is too narrowed to ensure that a right angle xcex8 is achieved with a control of the process parameters. Thus, problems of the stringer still occur.
It is therefore a primary objective of the present invention to provide a method of fabricating a flash memory to solve the above-mentioned problems.
It is another objective of the present invention to provide a method of fabricating a stringerless flash memory to achieve better reliability for the flash memory.
It is another objective of the present invention to provide a method of fabricating a stringerless flash memory to widen the process window.
It is still another objective of the present invention to provide a method of fabricating a flash memory with a T-shaped floating gate.
According to the claimed invention, a silicon oxide layer is formed on a semiconductor substrate. A plurality of rows of layer stacks are then formed on the silicon oxide layer with a shallow trench positioned between two adjacent layer stacks. Each layer stack includes a polysilicon layer and a sacrificial layer and has two side walls. In addition, each side wall of the layer stack intersects the bottom of the shallow trench at an angle of approximately 90 degrees. Following this, a high density plasma chemical vapor deposition (HDPCVD) silicon oxide layer is formed to cover the layer stacks and the shallow trenches. Then, the HDPCVD silicon oxide layer is planarized to expose the sacrificial layer. After the complete removal of the sacrificial layer, an insulating layer and a word line layer are formed, respectively, on the polysilicon layer followed by forming a photoresist layer on the word line layer to define a position for forming a word line. Subsequently, a first dry etching process is performed to remove portions of the word line layer not covered by the photoresist layer with a first selectivity of polysilicon to silicon oxide. Then, a second dry etching process is performed to etch portions of the insulating layer not covered by the photoresist layer with a second selectivity of polysilicon to silicon oxide. Finally, a third dry etching process is performed to etch the polysilicon layer with a third selectivity of polysilicon to silicon oxide.
It is an advantage of the present invention that a three-step etching process is used to form a T-shape side view for the polysilicon layer, preventing polysilicon from remaining on the side wall of the HDPCVD silicon oxide layer. Etching machines with a source power supply and a bias power supply, such as DPSPoly etcher of Applied Materials Co., are used in the third etching process. An etching gas, having a mixture of 90% to 95% HBr and 5% to 10% Hexe2x80x94O2 is also suggested for the third etching process. In addition, the source power supply ranges from 300 to 600 Watts, the bias power supply ranges from 70 to 150 Watts, and a pressure ranges from 50 to 100 Torrs. Under this environment, a better lateral etching ability is provided in the third etching process to effectively prevent occurrence of stringers.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.